Job Description and Requirements
Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything?where devices are getting smarter, everything's connected, and everything must be secure.
Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at the forefront of Smart, Secure Everything with the world's most advanced tools for silicon chip design, verification, IP integration, and application security testing. Our technology helps customers innovate from Silicon to Software, so they can deliver Smart, Secure Everything.
Founded in 1986, $3B+ Synopsys employs 13,000+ headquartered in Mountain View, California, located globally in over 25 countries with 113+ offices throughout North America, Europe, Japan, Asia, the Pacific Rim, India and Israel.
Synopsys is committed to fostering an environment that treats people with respect, honesty and professionalism. We're also committed to partnering with the communities in which we work. Every year, Synopsys reaches out to local communities with resources and employee leadership to support education, science programs and a variety of other activities.
Come and be part of a collaborative team environment that innovates and develops the latest IP solutions that enable the way the world designs. Join US!
Synopsys is hiring an experienced
RTL Designer
to work with us to develop digital RTL Verilog designs with focus on DDR.
In this role you will be responsible for:
Generating and reviewing design specifications, developing implementation architectures.
Developing, coding, debugging, maintaining, and supporting RTL for significant portions of our designs.
Generating documentation for customers, circuit development, test planning, verification environments, and usage.
Ideal candidate will:
Have a passion for creating solutions with a strong interest to continue being the best in the world at what we do.
Have 8+ years of expert experience in digital RTL development and debugging, with an unyielding drive to take responsibility for increasingly complex designs.
Possess a strong desire to learn and explore new technologies.
Demonstrate good analysis, communication, and problem-solving skills.
Have prior knowledge of and experience in ASIC design and associated development environments.
Be fluent in synthesizable Verilog, comfortable with Perl, familiar with C, and experience with digital simulation and debug using industry-standard tools.
The base salary range across the U.S. for this role is between $164,000 - $246,000. In addition, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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