Join the leading chiplet startup! As an Eliyan Physical Design Director, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PnR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits. ONSITE M-F
\n Key Responsibilities:Lead and manage a team of physical design engineers, providing technical direction, mentorship, and performance feedback.Define and execute the physical design strategy for multiple projects, ensuring alignment with company goals and timelines. Develop, optimize, and maintain ASIC design flows for synthesis, PnR, EM/IR analysis, STA, and PV. Drive continuous improvements in flow efficiency, automation, and quality metrics to meet power, performance, and area (PPA) targets. Own the complete ASIC physical design process, from RTL handoff to GDSII delivery. Collaborate with front-end design teams on RTL readiness and design-for-test (DFT) requirements. Oversee logic synthesis, ensuring adherence to timing, power, and area constraints. Drive floor planning, placement, clock tree synthesis (CTS), routing, and physical optimization in PnR. Manage EM/IR analysis, timing closure through STA, and physical verification, including DRC, LVS, and metal fill. Ensure successful tapeout with full sign-off criteria met, including reliability and manufacturability requirements. Work closely with cross-functional teams, including front-end design, DFT, package engineering, and manufacturing.Present project updates and status reports to executive leadership. Minimum Qualifications:Expertise in multiple areas of physical design, timing, and signoff. Strong scripting and automation skills. Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. Ideal Qualifications:12+ years of experience in ASIC physical design, with a proven track record of leading teams through successful tapeouts. Deep expertise in the following areas: o RTL-to-GDSII flows o Synthesis, PnR, STA, EM/IR, and PV o Physical design for advanced process node (5nm and below) across two or more foundries.Strong knowledge of EDA tools (Synopsys or Cadence) and scripting (Python, Perl). Exceptional leadership, project management, and problem-solving skills.
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