Responsible for developing physical design methodologies and customizing recipes across
various implementation steps to optimize PPA (power, performance and area). Develop physical
design methodologies and customizing recipes for all the steps being involved during synthesis,
placement, clock tree synthesis, and route in addition to developing the utility either through
regular place-and-route tool capability or through any in-house tool. Own block level design of
CPU Core/L2 blocks from RTL-to-GDSII which include synthesizing the behavior RTL to gate
level netlist, performing block level floorplan, and arranging the mega cell placement, placing
the gate level design to optimize for timing and power requirement, performing clock tree
synthesis, and distributing the clock network to minimize clock skew and latency. Discuss and
collaborate with micro-architects on topics related to feasibility studies and explore PPA
tradeoffs for design closure. Find design solutions to optimize timing and power collaboratively
and develop internal tools to solve design issues and help analysis. Run static timing analysis
with the final netlist and extracted RC to guarantee timing closure. Run power analysis to
guarantee power closure and verify electrical migration according to the current and power
models. Verify the design rule and layout versus schematic check to guarantee the
manufacturing quality and work with a multi-functional engineering team to implement and
validate physical design by running all signoff flows such as Timing, Power, EM, IR, and
PDV.
\n Education:Master's or foreign equivalent in Electrical Engineering, Computer Engineering, or related field Experience: 6 months of experience in job offered or related occupation. Special Requirements:Must have at least 6 months of prior work experience in each of the following:HDL languages including Verilog.Scripting Languages Perl and TCL.Digital logic gates, encompassing both combinational and sequential aspects, along with theirrespective transistor implementations.
**Telecommuting allowed for this position**
\n$156,624 - $177,500 a year
\nWorksite:3315 Scott Blvd, Floor 4, Santa Clara, CA 95054 Applicant Instructions: Email resume to: ******** . Include job code 91836 in reply. EOE.