Principal Engineer - Hbm Soc Design And Integration - Tpg

Our vision is to transform how the world uses information to enrich life forall.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Our Opportunity Summary:

For more than 43 years, Micron Technology, Inc. has redefined innovation with the world's most advanced memory and semiconductor technologies. We're an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life.

As an HBM SOC Design and Integration Engineer, you will be responsible for the design & development of next-generation HBM DRAM products. You will be part of a highly multi-functional team of technical domain experts collaborating closely with a distributed team of Design Engineering, Product Engineering, Process Development, Package Engineering & Business Units to implement a common goal of ensuring our future HBM roadmap is successful. You will apply your deep understanding of SOC Architecture, RTL Logic Design, IP Integration, high-speed interface design, high-performance computing architectures, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative architectures to target best-in-class performance, power, cost, reliability and quality for Micron's HBM product portfolio.

In HBM HIG (High Bandwidth Memory – Heterogenous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, simulation, testing, debugging and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only while the Logic chip can use a full ASIC flow. Lastly, verification and testing (validation) of HBM is the most challenging due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.

What's Encouraged Daily:

Analyze customer requirements and specification documents, work with IP vendors to select off-the-shelf IPs, and modify or custom design new ones if needed.

Review architectural specifications and provide constructive feedback to help create high-quality specifications.

Efficiently and productively execute project deliverables, whether writing specifications, developing RTL, integrating IP, testing code, debugging failures, running static checks and resolving issues identified by static checks.

Proactively identify and flag quality issues, performance problems, and opportunities to reduce power consumption in architecture, microarchitecture, RTL, or circuits.

Collaborate with the verification team by reviewing test plans, assisting with writing assertions and coverage monitors, and providing feedback and suggestions for test changes.

Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.

Engage with customers to support issues with current HBM architectures and find opportunities to innovate on future HBM solutions.

How To Qualify:

Proficiency in microarchitecture and high-quality RTL development with the ability to write and test code in System Verilog.

Experience with automating IP integration using standards such as IP-XACT and tools such as Coretools, Defacto etc..

Experience with using register description languages such as SystemRDL.

Experience with SOC integration methods such as DFT/MBIST, CDC, and static LP checks.

Experience dealing with clock domain crossings (CDC).

Experience with SOC interconnects and bus standards like AMBA AXI, ACE, APB, AHB, etc.

Ability to write assertions using SVA.

Understanding of how to optimize a design for performance and low power consumption and how to use UPF.

Good knowledge of static timing analysis, synthesis design constraints, and how to close timing by using logic techniques, false path constraints, and multi-cycle path constraints.

Understanding of design for testability concepts such as MBIST and scan and how to write RTL for testability.

Proven track record of innovation and problem-solving in high-performance and/or low power SOC development.

7+ years of relevant job/skill-related experience.

Experience delivering highly technical solutions.

What Sets You Apart:

BSEE or higher.

Proven track record of innovation and problem-solving in high-performance and/or low power SOC development.

Familiarity with DRAM operation and JEDEC specifications, preferably with the HBM product family.

Familiarity with scripting languages such as Python.

Experience with working on one or more of the following IPs: UCIE, Memory Controller, NOCs.

Experience with NOC generation tools.

Experience in any of the following focus areas: memory array architectures, on-die and off-die high-speed signaling, PHY & interface development, power delivery network planning and optimization, power consumption reduction, CMOS requirements identification, packaging technologies, and thermal modeling.

Good verbal and written communication skills with the ability to efficiently synthesize and convey sophisticated technical concepts to other partners and leadership.

A self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds.

An innovative approach that is open to improving upon any of our processes or products.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays.For additional information regarding the Benefit programs available, please see the Benefits Guide posted onmicron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

To learn about yourright to work click here.

To learn more about Micron, please visitmicron.com/careers

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization ****** 1-800-336-8918 (select option #3)

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.