Join the leading chiplet startup!
As an Eliyan digital verification engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet based systems with best-in-class power, area, manufacturability, and design flexibility.
You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs and Controllers.
You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.
We offer a fun work environment with excellent benefits.
Key ResponsibilitiesDevelop and execute verification plans for Ethernet PCS/PMA IPs for various speeds (100/200/400/800G)Create and maintain SystemVerilog/UVM-based verification environmentsWrite and debug SystemVerilog/UVM compliant test cases for block and chip levelMaintain a regression environment for enabling design CI/CD pipelinesCollaborate with design engineers to ensure design quality with continuous micro-architecture, test-plan, and coverage reviewsDevelop, maintain, and track various test plan items and progress towards RTL freezeStay up to date with industry trends, emerging technologies and progress in standards' bodiesEnsure IP compliance with Ethernet standards (IEEE 802.3)Integration 3rd party VIPs and coordinate feature/bug tracking requestsCreate, improve, maintain DPI based FW simulation environmentsCreate, improve, maintain GLS environments for functional and power simulations QualificationsBachelors or Masters or Ph.D in Electrical Engineering and related fields, or equivalent8+ years of experience in verification of serial transmission protocols and products (preferably in retimer, gearbox, Ethernet PMA/PCS logic)Strong expertise in UVM, test environment and assertion coding with SystemVerilogProficiency in 3rd party tools for regression management and coverage analysisKnowledge of Ethernet 802.3 standards' clauses related to 100G/200G/400G/800G, Auto-Negotiation and Link TrainingStrong bias for innovations across all aspects of digital verification including automation of mundane activities and methods for quality improvementExperience in verifying 3rd party mixed signal IPs as well as integration of VIPsProven track record of being part of a start-up like environmentKnowledge of DRAM Controllers/PHYs and HBM Memory a plus
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