Senior Digital Design Engineer

Job Description:
Define block level micro-architecture and write design specificationRTL implementation of the specification while meeting power, area, timing constraintsWork with Verification team to verify functionalityWork with Backend team to go through ASIC flow to tape-out successWork with Firmware teams to develop APIs and help silicon bring upPost-silicon validation and debugMinimal Qualifications:
Master's degree in Electrical Engineering or related field10 years of industrial experience in ASIC DesignExperience in micro-architecture and RTL design of complicated blocksProficient in RTL design using HDLFamiliar with design and verification tools (VCS, Verdi, DC, etc.
)Hands on experience of ASIC design flow including RTL design, verification, Lint, CDC, LEC, logic synthesis, DFT, timing analysis, floor-planning, GLS, ECO, bring-up & lab debugProficient scripting language in one of: Python, TCL, Shell, PerlSelf-motivated team workerPreferred Qualifications:
Hands on design experience in PCIe logical / link / transaction layers.Knowledge of PCIe / CXL Protocol Stacks, especially latest GenerationsExperiences in SerDes architecturesExperiences in Digital Signal ProcessingGood debugging and problem-solving skills
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