Senior Isp Rtl Design Manager

Responsibilities: Responsible for implementing ISP Algorithm into HW using Verilog, SystemVerilog and/or SystemC (High Level Synthesis)Define ISP HW Architecture based on product features and performance requirements, also with gate count and power estimationVerify Logic at ISP level and Digital System levelOptimize Design for less gate count and low power consumptionDrive ISP Design activities in close collaboration with ISP Algorithm Team, ISP Design leaders in other sites, and Digital System Design TeamLeading, supervising and mentoring a team of RTL design engineersRequirements: Minimum MSEE, or BSEE, or equivalent, plus 7+ years of Digital Design and verification related experience3+ years project management / people management experience / skillExperience / knowledge in CMOS Image Sensor and image signal processing (ISP)Experience / knowledge in System C/C++, System Verilog, and Catapult HLS tool.Ability to lead teams and collaborate effectively with people in different functionsStrong time management skills to ensure timely completion of deliverablesGood communication and interpersonal skillsResult oriented and embrace change behaviours

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