Senior Physical Design Engineer (Contract, Hybrid)

Details of the offer

Senior Physical Design Engineer Sunnyvale, CA (Onsite/Hybrid)
Start Date: November or December
Work Status: US Citizen only
Hourly Rate: $80-$90 on 1099 or C2C
6-12 months contract with possible extensions

The ideal candidates should be highly proficient in using all the Synopsys EDA tools/flows with little to no ramp-up time needed to make an immediate impact. You will be responsible for doing all aspects of SOC Physical Design implementation.

Required Qualifications: Experience: 10+ years Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS) Synopsys DC, DCG, DC TOPO Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by customer's Physical Design Implementation team members Familiar with Synopsys Lynx a plus RTL Hand-over experience a plus for RTL to GDS Experience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioning Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches) Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-off Ability to define sign-off requirements/margins based on Foundry technology requirements a plus DFT experience with compression, scan, TDF, and MEMBIST a plus Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC) Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR) Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus Experience with GlobalFoundries, TSMC, & Samsung technology nodes are a plus Consultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out
#J-18808-Ljbffr


Nominal Salary: To be agreed

Source: Jobleads

Job Function:

Requirements

Senior Systems Engineer (Onsite)

Date Posted: ******** Country: United States of America Location: CA601: Goleta (EW) Bldg H01 6380 Hollister Avenue Building H01, Goleta, CA, 93117 USA Po...


Raytheon - California

Published 6 days ago

Electronic Warfare Integrated Product Team Lead (Onsite)

Date Posted: ******** Country: United States of America Location: CA601: Goleta (EW) Bldg H01 6380 Hollister Avenue Building H01, Goleta, CA, 93117 USA Po...


Raytheon - California

Published 6 days ago

Infrared Semiconductor Product Engineer

Date Posted: ******** Country: United States of America Location: CA602: Goleta (RVS) Bldg B01 6825 Cortona Drive Building B01, Goleta, CA, 93117 USA Posi...


Raytheon - California

Published 6 days ago

Maintenance Technician, Multifamily

Since 2006, Southwest Equity Partners has been connecting tenants with multi-family and commercial properties throughout San Diego, California. Each and ever...


Southwestep - California

Published 6 days ago

Built at: 2024-11-15T04:49:30.311Z