Senior Physical Design EngineerWork Status: US Citizen only
6-12 months contract with possible extensions
The ideal candidates should be highly proficient in using all the Synopsys EDA tools/flows with little to no ramp-up time needed to make an immediate impact.
You will be responsible for doing all aspects of SOC Physical Design implementation.
Required Qualifications:Experience: 10+ yearsSynopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/ERC/PERC/LVS)Synopsys DC, DCG, DC TOPOSynopsys Flow Development & SOC implementation methodologies that will be deployed and used by customer's Physical Design Implementation team membersFamiliar with Synopsys Lynx a plusRTL Hand-over experience a plus for RTL to GDSExperience with top-level floorplanning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floorplanning/partitioningSolid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches)Highly proficient with SDC STA constraints development driving back-end tools for blocks and full-chip through timing closure & sign-offAbility to define sign-off requirements/margins based on Foundry technology requirements a plusDFT experience with compression, scan, TDF, and MEMBIST a plusSynopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flowsFamiliar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPFSynopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC)Ansys Redhawk SC (For IR analysis for static, dynamic, & EMIR)Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plusExperience with GlobalFoundries, TSMC, & Samsung technology nodes are a plusConsultants should have a solid track record on execution delivering to high-quality standards for delivering to high quality tape-out
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