Join a cutting-edge and well-funded hardware startup in Silicon Valley as a Junior Power-Management Architect, focused on modeling and optimizing Power/Performance features on a cutting-edge design. Our mission is to reimagine silicon and create Risc-V based Accelerated computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world.
\n ResponsibilitiesWork closely with the Performance team to analyze power behavior of workloads of interest on Rivos' architectureDefine and extend the power management features, to maximize performance on workloads of interest under power and current constraintsWork closely with micro architecture and design teams to bring the new features to product level qualityCollaborate with the performance simulation teams to prototype the features and analyze their benefits pre-siliconWork closely with the FW and SW teams to integrate the heuristics into the FW code and simulation modelAssist with post-silicon bringup and characterization of the power-management architecture on RIvos' devices. RequirementsBS/MS degree in CS/CE/EE or equivalent experienceExperience with CPU/GPU/SoC power-management architecture feature definition such as power capping, thermal control, current capping, and DVFSGood understanding of power and/or performance modeling using simulators is preferredAbility to work collaboratively in a fast-paced and dynamic environmentGo-getter capable of initiating and driving tasks from start to finish with minimum technical oversight Education and ExperienceBS (5-10 years of experience) or MS (3-5 years of experience) with a degree in CS/CE/EE or equivalent field, The team already includes senior engineers who will collaborate on feature definition and mentoring.
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