SoC Physical Design Engineer, STA/TimingImagine what you could do here!
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In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SoC using state of the art process technology.
Description: Work with design teams to understand and debug constraints, facilitate logic changes to improve timing.Work with Physical Design team highlighting issues and best practices.Help create timing ECOs for project tapeout.Create and maintain scripts and methodologies for analysis and runs.Create documentation and help with guidelines/specs.Deep analysis of timing paths to identify key issues.Implement timing infrastructure.Key Qualifications: Minimum BS and 10+ years of relevant industry experience.Familiar with all aspects of timing of large high-performance SoC designs in sub-micron technologies.Expert in STA and methodologies for timing closure, and have a deep understanding of noise, crosstalk, and OCV effects among others.Familiar with circuit modeling including SPICE models and worst-case corner selection.Strong programming skills with Perl and TCL.Experience with large design STA and Timing Closure.Expert in ECO techniques and implementation.Good communicator who can accurately describe issues, propose solutions, and drive them through completion.Education & Experience: Minimum BS and 10+ years of relevant industry experience.
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