We are looking for a talented and passionate Senior FPGA Design Engineer to be part of an exciting team. You will have an enormous opportunity to make a large impact on the design, architecture, and implementation of cutting-edge scientific products used for scientific discovery. We provide innovative products that expand the research and diagnostic capabilities of our customers by delivering simple, affordable solutions. You'll work in Electrical Engineering Group and collaborate with software developers, systems engineers, product managers, scientists, technical program managers, and other engineering teams. You'll create extendable design and easy to maintain solutions with the long-term vision in mind.
How You'll Make An Impact: Design, develop, and test FPGA based systems, used to control scientific instruments.Development of new features for scientific embedded systems.Investigate, prototype, and deliver new and innovative system solutions.Work with electrical, mechanical, software and system engineers to develop the requirements.Participate in design reviews, and documentation.Deliver investigation plans and reports, architectural documents, design specs, and FPGA source code, build scripts.Perform tasks including debug, bring-up, Beta and production FPGA development.Collaborate with both software and hardware product teams.What You Bring: Required:
Bachelor's degree or higher in Electrical Engineering or related field5+ years of experience as an FPGA design engineerProficient in at least one design language (Verilog or VHDL). Proficiency in both languages is a plus.Timing Analysis, including timing delays along the paths in your design and comparing them against the specified timing constraints, creating accurate timing constraints is essential, establishing timing exceptions where necessary, validating constraints at each stage of the design flow. Use of Validation Tools like Vivado's report_timing_summary, check_timing, and report_clocks to validate your constraints.Experience in Place and Route (P&R) Timing Closure: Achieving timing closure involves iterative steps, incremental design, setting up constraints and identify issues such as clock domain crossing. Optimize placement, routing, and physical design for performance and resource utilization in a highly complex FPGA designSuccessful tracks in delivered products with high-speed ADC interfaces such as LVDS, JESD204, ensure proper impedance matching, signal integrity, and noise immunity.Experience in one or more of these areas: cameras, sensors, motor control, ADC/DAC, I2C, RS485, LVDS, Ethernet, SPI communication protocols.System level integration experience.Board brings up experience.Ability to understand, debug and work with Schematics.Preferred:
Strong debugging/troubleshooting and problem-solving skills of embedded systemsExperience with Quartus software and Altera/Intel Stratix and MAX family FPGAKnowledge in serial interface protocols like I2C, SPIExperience with motion control, LASER, PMT, pumps, valves, liquid handling, and other sensors.Experience in writing embedded firmware for Microcontrollers and C/C++ programming.
#J-18808-Ljbffr
