Uvm/ Systemverilog Design Verification Engineer

Job Description:

As a Verification Engineer, you will own functional verification for a custom controller. You will develop functional verification infrastructure to ensure functional correctness of a design as well as improve the throughput of the verification effort.

In this role, you will develop test plans for functional units and subsystems. You will analyze coverage from various dimensions and develop monitors and checkers for better quality assurance. In the final stages, you will also run GLS related simulations.

Responsibilities:

Work closely with the architecture and RTL designers on verifying the functionality correctness of the design.

Reviewing the architecture and design specification. Define test environment and test plans at both IP and chip level.

Execute the test plan, including test development, reference model design, and failure debug, contribute to the development of overall verification infrastructure and tools.

UVM/python test development for driving VIPs and other stimulus drivers.

of test components such as monitors, scoreboards, and python models.

Coverage closure and GLS bring up and testing.

Experience:

4+ years experience as verification engineer with SystemVerilog, UVM, and functional coverage.

Knowledge of digital logic design, CPU/SOC architecture and microarchitecture

2+ years of Python and Linux experience

Experience developing and maintaining verification testbenches, test cases, and test environments.

Experience in all aspects of verification life cycle, specifically, SDF and GLS simulations.

Experience in ethernet and SPI required.

Knowledge of general-purpose operating systems such as Linux and Android.

About US Tech Solutions:

US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to , , , sex, , , , , or status as a protected veteran.