Memory Subsystem Intern

Our mission is to create computing platforms (HW/SW co-design) that will transform the industry with the most advanced technologies. As a memory subsystem intern, you will be given a project to work on SOC-level performance per watt improvement through memory management innovations. You will be working with the internal SW (eg. OS, Kernel, Framework) and Silicon (eg. RTL, Power, Perf) team members
\n RequirementsKnowledge in one or more of the following areas,  memory subsystem design, cache memory, LPDDR/DDR/HBM/CXL memory. Knowledge and experience with common LLM (Large Language Model) workloads. Proficiency in System Verilog, C or C++, scripting languages such as Python.Experience with high-level simulators for performance or power estimation is a plus.Knowledge in server-class GPU/ML architecture is a plus. ResponsibilitiesResponsible for an analytical model of LLM inference and training memory usageResponsible for running the performance simulation to extract the workload's memory footprint and bandwidth requirement. Hence, to derive the energy cost of memory data movement Responsible for identifying memory subsystem capacity or bandwidth bottlenecks and improve the performance and energy efficiency Minimum Education & ExperienceCurrent EE or CS master or Ph.D students with computer architecture backgrounds
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