Staff SoC Design Integration & Synthesis EngineerSan Jose or Irvine
InnoPhase Inc., DBA GreenWave Radios, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.
Based in San Diego, California, GreenWave Radios has earned a reputation for delivering power-efficient digital-to-RF solutions. Our commitment to innovation is backed by a robust team of more than 100 talented engineers spread across four R&D facilities worldwide and an extensive portfolio of over 120 global patent filings, underscoring our dedication to pushing the boundaries of radio technology.
As a Staff Engineer, SoC Design/Integration & Synthesis in the VLSI Engineering Group, you will support and enhance physical design EDA tools and process digital design flows using Cadence tools. You must possess the necessary digital design skills and programming flow knowledge to allow engineers to support, develop, and enhance the EDA and support tools and develop new custom scripts and reports. You will perform PnR implementation of high-performance SoC designs, including logic synthesis, floorplan and powerplan, power domain specification, place and route, clock tree synthesis, static timing analysis, IR drop analysis, EM, DRC, and physical verification in advanced CMOS technology nodes. You will work closely with a multi-site team of VLSI design, verification, and software engineers to deliver production-quality designs with embedded Linux-based wireless communications to enable our market-leading cellular infrastructure radio solutions.
This position can be based in San Jose, CA or Irvine, CA.
Key Responsibilities Develop custom EDA tool enhancements using scriptingFrontline support for the design team for debugging and developing productivity enhancementsMaintain, install, and upgrade existing CAD toolsConfigure and install foundry PDKsProactively drive and resolve tool bugsInteract with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functionsAssist in tape out process, including DRC, LVS, and ERC verification flowsWork with the RTL and System design teams to drive the physical design of the device in the early design cycleDesign, implement, and verify suitable methodology that meets the QoR goalsResolve design and flow issues related to the physical design, identify potential solutions, and drive execution.Deliver physical design of entire SoC, complete with specification, flow, and automationInterface with the RTL design team to drive design modifications to resolve physical design issues and implement ECOsUse EDA tool-based programming and scripting techniques to automate and improve throughput and qualityJob Requirements BSEE and a minimum of ten years of back-end physical design experience requiredDeep knowledge of PNR/Synthesis tools, flows and methodologiesHands-on experience with scripting and software development tools (Python, Tcl, C++)Highly capable in Linux/Unix operating systemsWorking knowledge of IC management revision control - GITUnderstanding of SCAN ATPG, MBIST, Logic BIST, DFT/DFM, and fault coverage analysisProven knowledge of System Verilog/UVM methodology and other advanced design verification techniquesExperience with DRC/LVS and extraction flow and rules decksFamiliarity with compute server grid systems and server load balancing solutionsFamiliarity with job monitoring and related software workload tracking toolsExcellent MS Office skills, Excel, Word, and PowerPoint, including VBA, Python scriptingExcellent verbal and written communication skillsTeam player with a passion for quality and a strong sense of urgency and pride in their workExpert in Cadence Innovus, Genus, Tempus, and Voltus environmentsDeep experience in Cadence Virtuoso Design Framework, including flow automation with various EDA tools and PDKsCompensation and Benefits: Our compensation package at InnoPhase, dba GreenWave Radios, includes base pay and pre-IPO stock options. The base pay range for this role is between $140K and $225K. Your base pay will depend on the market, interview results, skills, qualifications, experience, education, and location. Our employee benefits include a comprehensive group health plan, matching 401(k), training reimbursement, and various paid leaves (vacation, sick leave, holidays, maternity/paternity leave, jury). Visit our website to learn more about our employee benefits.
#J-18808-Ljbffr